////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: M.81d
//  \   \         Application: netgen
//  /   /         Filename: NbitPipelinedAdder_synthesis.v
// /___/   /\     Timestamp: Sat Apr 02 14:03:59 2011
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim NbitPipelinedAdder.ngc NbitPipelinedAdder_synthesis.v 
// Device	: xc3s500e-5-fg320
// Input file	: NbitPipelinedAdder.ngc
// Output file	: C:\peter\enee408\pipeline_ripple_carry_adder\netgen\synthesis\NbitPipelinedAdder_synthesis.v
// # of Modules	: 1
// Design Name	: NbitPipelinedAdder
// Xilinx        : C:\Xilinx\12.4\ISE_DS\ISE\
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module NbitPipelinedAdder (
  c_out, clock, c_in, s_out, y_in, x_in
);
  output c_out;
  input clock;
  input c_in;
  output [7 : 0] s_out;
  input [7 : 0] y_in;
  input [7 : 0] x_in;
  wire [4 : 4] \reg_input_a<1> ;
  GND   XST_GND (
    .G(\reg_input_a<1> [4])
  );
  OBUF   c_out_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(c_out)
  );
  OBUF   s_out_7_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[7])
  );
  OBUF   s_out_6_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[6])
  );
  OBUF   s_out_5_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[5])
  );
  OBUF   s_out_4_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[4])
  );
  OBUF   s_out_3_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[3])
  );
  OBUF   s_out_2_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[2])
  );
  OBUF   s_out_1_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[1])
  );
  OBUF   s_out_0_OBUF (
    .I(\reg_input_a<1> [4]),
    .O(s_out[0])
  );
endmodule


`ifndef GLBL
`define GLBL

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule

`endif

